PIC18F2585_07 Datasheet, PDF (165/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
15.0 CAPTURE/COMPARE/PWM
(CCP1) MODULES
PIC18F2585/2680 devices have one CCP1 module.
PIC18F4585/4680 devices have two CCP1
(Capture/Compare/PWM) modules. CCP1, discussed in
this chapter, implements standard Capture, Compare
and Pulse-Width Modulation (PWM) modes.
ECCP1 implements an Enhanced PWM mode. The
ECCP1 implementation is discussed in Section 16.0
“Enhanced Capture/Compare/PWM (ECCP1)
Module”.
The CCP1 module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP1 module operation in the
following sections is described with respect to CCP1,
but is equally applicable to ECCP1.
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP1
modules. The operations of PWM mode, described in
Section 15.4 “PWM Mode”, apply to ECCP1 only.
REGISTER 15-1:
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
—
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 for CCP1 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC19:DC12) of the duty cycle are found in ECCPR1L.
CCP1M3:CCP1M0: CCP1 Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge or CAN message received (time-stamp)⁽¹⁾
0101 = Capture mode, every rising edge or CAN message received (time-stamp)⁽¹⁾
0110 = Capture mode, every 4th rising edge or every 4th CAN message received
(time-stamp)⁽¹⁾
0111 = Capture mode, every 16th rising edge or every 16th CAN message received
(time-stamp)⁽¹⁾
1000 = Compare mode: initialize CCP1 pin low; on compare match, force CCP1 pin high
(CCPIF bit is set)
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP1 pin low
(CCPIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPIF bit is set,
CCP1 pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer (TMR1 or TMR3, CCP1IF bit is set)
11xx = PWM mode
Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 163