PIC18F2585_07 Datasheet, PDF (336/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
Table 23-3 shows the relation between the clock
generated by the PLL and the frequency error from jitter
(measured jitter-induced error of 2%, Gaussian distribu-
tion, within 3 standard deviations), as a percentage of
the nominal clock frequency.
This is clearly smaller than the expected drift of a crystal
oscillator, typically specified at 100 ppm or 0.01%. If we
add jitter to oscillator drift, we have a total frequency drift
of 0.0132%. The total oscillator frequency errors for
common clock frequencies and bit rates, including both
drift and jitter, are shown in Table 23-4.
TABLE 23-3: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS
PLL
Output
P_jitter
T_jitter
Frequency Error at Various Nominal Bit Times (Bit Rates)
8 μs
(125 Kb/s)
4 μs
(250 Kb/s)
2 μs
(500 Kb/s)
1 μs
(1 Mb/s)
40 MHz
24 MHz
16 MHz
0.5 ns
0.83 ns
1.25 ns
1 ns
1.67 ns
2.5 ns
0.00125%
0.00209%
0.00313%
0.00250%
0.00418%
0.00625%
0.005%
0.008%
0.013%
0.01%
0.017%
0.025%
TABLE 23-4: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS
(100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER)
Frequency Error at Various Nominal Bit Times (Bit Rates)
Nominal PLL Output
8 μs
(125 Kb/s)
4 μs
(250 Kb/s)
2 μs
(500 Kb/s)
1 μs
(1 Mb/s)
40 MHz
24 MHz
16 MHz
0.01125%
0.01209%
0.01313%
0.01250%
0.01418%
0.01625%
0.015%
0.018%
0.023%
0.02%
0.027%
0.035%
DS39625C-page 334
Preliminary
© 2007 Microchip Technology Inc.