PIC18F2585_07 Datasheet, PDF (476/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
Timer0 .............................................................................. 147
Associated Registers ............................................... 149
Clock Source Edge Select (T0SE Bit) ...................... 148
Clock Source Select (T0CS Bit) ............................... 148
Operation ................................................................. 148
Overflow Interrupt .................................................... 149
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 148
Timer1 .............................................................................. 151
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .................................................................. 153
Layout Considerations ..................................... 154
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 154
Special Event Trigger (ECCP1) ............................... 174
Use as a Real-Time Clock ....................................... 154
Timer2 .............................................................................. 157
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt .......................... 169, 175
Timer3 .............................................................................. 159
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .................................................. 151, 159, 161
Overflow Interrupt .................................... 151, 159, 161
Special Event Trigger (CCP) .................................... 161
TMR3H Register .............................................. 151, 159
TMR3L Register ............................................... 151, 159
Timing Diagrams
A/D Conversion ........................................................ 450
Acknowledge Sequence .......................................... 220
Asynchronous Reception ......................................... 239
Asynchronous Transmission .................................... 237
Asynchronous Transmission (Back to Back) ........... 237
Automatic Baud Rate Calculation ............................ 235
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................. 240
Auto-Wake-up Bit (WUE) During Sleep ................... 240
Baud Rate Generator with Clock Arbitration ............ 214
BRG Overflow Sequence ......................................... 235
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 223
Brown-out Reset (BOR) ........................................... 436
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 224
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 224
Bus Collision During a Start
Condition (SCL = 0) ......................................... 223
Bus Collision During a Start
Condition (SDA Only) ....................................... 222
Bus Collision During a Stop
Condition (Case 1) ........................................... 225
Bus Collision During a Stop
Condition (Case 2) ........................................... 225
Bus Collision for Transmit and Acknowledge ........... 221
Capture/Compare/PWM (CCP) ................................ 438
CLKO and I/O .......................................................... 435
Clock Synchronization ............................................. 207
Clock/Instruction Cycle .............................................. 65
EUSART Synchronous Receive
(Master/Slave) ................................................. 448
EUSART Synchronous Transmission
(Master/Slave) ................................................. 448
Example SPI Master Mode (CKE = 0) ..................... 440
Example SPI Master Mode (CKE = 1) ..................... 441
Example SPI Slave Mode (CKE = 0) ....................... 442
Example SPI Slave Mode (CKE = 1) ....................... 443
External Clock (All Modes Except PLL) ................... 433
Fail-Safe Clock Monitor ........................................... 356
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect ......................................... 270
I²C Bus Data ............................................................ 444
I²C Bus Start/Stop Bits ............................................ 444
I²C Master Mode (7 or 10-Bit Transmission) ........... 218
I²C Master Mode (7-Bit Reception) .......................... 219
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 204
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 209
I²C Slave Mode (10-Bit Transmission) .................... 205
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
I²C Slave Mode (7-Bit Transmission) ...................... 203
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 210
Master SSP I²C Bus Data ........................................ 446
Master SSP I²C Bus Start/Stop Bits ........................ 446
Parallel Slave Port (PIC18F4585/4680) ................... 439
Parallel Slave Port (PSP) Read ............................... 145
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 184
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 184
PWM Direction Change ........................................... 181
PWM Direction Change at Near
100% Duty Cycle ............................................. 181
PWM Output ............................................................ 169
Repeat Start Condition ............................................ 216
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 436
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
(Master Mode, SREN) ..................................... 244
Synchronous Transmission ..................................... 242
Synchronous Transmission (Through TXEN) .......... 243
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
DS39625C-page 474
Preliminary
© 2007 Microchip Technology Inc.