PIC18F2585_07 Datasheet, PDF (398/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Enter Sleep mode
SLEEP
None
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD
TO, PD
0000 0000 0000 0011
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
1
1
Q2
No
operation
Q3
Process
Data
Q4
Go to
Sleep
Example:
SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO = 1 †
PD = 0
† If WDT causes wake-up, this bit is cleared.
SUBFWB
Subtract f from W with Borrow
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
SUBFWB f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) – (f) – (C) → dest
N, OV, C, DC, Z
0101 01da ffff ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBFWB REG, 1, 0
Before Instruction
REG
W
C
=3
=2
=1
After Instruction
REG
W
C
Z
N
= FF
=2
=0
=0
= 1 ; result is negative
Example 2:
SUBFWB REG, 0, 0
Before Instruction
REG
W
C
=2
=5
=1
After Instruction
REG
W
C
Z
N
=2
=3
=1
=0
= 0 ; result is positive
Example 3:
SUBFWB REG, 1, 0
Before Instruction
REG
W
C
=1
=2
=0
After Instruction
REG
W
C
Z
N
=0
=2
=1
= 1 ; result is zero
=0
DS39625C-page 396
Preliminary
© 2007 Microchip Technology Inc.