PIC18F2585_07 Datasheet, PDF(51/482 Page) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

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PIC18F2585_07 Datasheet, PDF (51/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

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PIC18F2585/2680/4585/4680

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

TOSU

TOSH

TOSL

STKPTR

2585 2680 4585 4680

2585 2680 4585 4680

2585 2680 4585 4680

2585 2680 4585 4680

---0 0000

0000 0000

0000 0000

00-0 0000

---0 0000

0000 0000

0000 0000

uu-0 0000

---0 uuuu(3)

uuuu uuuu(3)

uuuu uuuu(3)

uu-u uuuu(3)

PCLATU

2585 2680 4585 4680 ---0 0000

---0 0000

---u uuuu

PCLATH

PCL

2585 2680 4585 4680

2585 2680 4585 4680

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PC + 2(2)

TBLPTRU

2585 2680 4585 4680 --00 0000

--00 0000

--uu uuuu

TBLPTRH

2585 2680 4585 4680 0000 0000

0000 0000

uuuu uuuu

TBLPTRL

2585 2680 4585 4680 0000 0000

0000 0000

uuuu uuuu

TABLAT

2585 2680 4585 4680 0000 0000

0000 0000

uuuu uuuu

PRODH

2585 2680 4585 4680 xxxx xxxx

uuuu uuuu

uuuu uuuu

PRODL

INTCON

INTCON2

INTCON3

2585 2680 4585 4680

2585 2680 4585 4680

2585 2680 4585 4680

2585 2680 4585 4680

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

uuuu uuuu

0000 000u

1111 -1-1

11-0 0-00

uuuu uuuu

uuuu uuuu(1)

uuuu -u-u(1)

uu-u u-uu(1)

INDF0

2585 2680 4585 4680

N/A

N/A

N/A

POSTINC0 2585 2680 4585 4680

N/A

N/A

N/A

POSTDEC0 2585 2680 4585 4680

N/A

N/A

N/A

PREINC0

2585 2680 4585 4680

N/A

N/A

N/A

PLUSW0

2585 2680 4585 4680

N/A

N/A

N/A

FSR0H

2585 2680 4585 4680 ---- 0000

---- 0000

---- uuuu

FSR0L

2585 2680 4585 4680 xxxx xxxx

uuuu uuuu

uuuu uuuu

WREG

2585 2680 4585 4680 xxxx xxxx

uuuu uuuu

uuuu uuuu

INDF1

2585 2680 4585 4680

N/A

N/A

N/A

POSTINC1 2585 2680 4585 4680

N/A

N/A

N/A

POSTDEC1 2585 2680 4585 4680

N/A

N/A

N/A

PREINC1

2585 2680 4585 4680

N/A

N/A

N/A

PLUSW1

2585 2680 4585 4680

N/A

N/A

N/A

FSR1H

2585 2680 4585 4680 ---- 0000

---- 0000

---- uuuu

FSR1L

2585 2680 4585 4680 xxxx xxxx

uuuu uuuu

uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read â0â.

6: This register reads all â0âs until the ECANâ¢ technology is set up in Mode 1 or Mode 2.

Â© 2007 Microchip Technology Inc.

Preliminary

DS39625C-page 49

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