PIC18F2585_07 Datasheet, PDF (291/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0 R/W-0
Mode 0 _{RXFUL(1) RXM1}
R/W-0
RXM0
U-0
R-0
R/W-0
— RXRTRRO FILHIT2
R-0
R-0
FILHIT1 FILHIT0
R/C-0
Mode 1, 2 _RXFUL(1)
bit 7
R/W-0
RXM1
R-0
RTRRO
R-0
FILHIT4
R-0
FILHIT3
R-0
FILHIT2
R-0
FILHIT1
R-0
FILHIT0
bit 0
bit 7
RXFUL: Receive Full Status bit⁽¹⁾
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared
by software after the buffer is read. As long as RXFUL is set, no new message will
be loaded and buffer will be considered full.
bit 6
Mode 0:
RXM1: Receive Buffer Mode bit 1
Combines with RXM0 to form RXM<1:0> bits (see bit 5).
11 = Receive all messages (including those with errors); filter criteria is ignored
10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’
01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’
00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register
Mode 1, 2:
RXM1: Receive Buffer Mode bit
1 = Receive all messages (including those with errors); acceptance filters are ignored
0 = Receive all valid messages as per acceptance filters
bit 5
Mode 0:
RXM0: Receive Buffer Mode bit 0
Combines with RXM1 to form RXM<1:0> bits (see bit 6).
Mode 1, 2:
RTRRO: Remote Transmission Request bit for Received Message (read-only)
1 = A remote transmission request is received
0 = A remote transmission request is not received
bit 4
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
FILHIT4: Filter Hit bit 4
This bit combines with other bits to form filter acceptance bits <4:0>.
bit 3
Mode 0:
RXRTRRO: Remote Transmission Request bit for Received Message (read-only)
1 = A remote transmission request is received
0 = A remote transmission request is not received
Mode 1, 2:
FILHIT3: Filter Hit bit 3
This bit combines with other bits to form filter acceptance bits <4:0>.
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 289