PIC18F2585_07 Datasheet, PDF (359/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
24.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2585/2680/4585/4680
MEMORY SIZE/DEVICE
48 Kbytes
(PIC18F2585/4585)
64 Kbytes
Address
(PIC18F2680/4680) Range
Block Code Protection
Controlled By:
Boot Block
Block 0
Boot Block
Block 0
000000h
0007FFh
000800h
003FFFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
Block 1
Block 2
Block 1
Block 2
004000h
007FFFh
008000h
00B7FFh
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
Unimplemented
Read ‘0’s
Block 3
00C000h
00FFFFh
010000h
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L —
—
—
—
CP3*
300009h CONFIG5H CPD
CPB
—
—
—
30000Ah CONFIG6L —
—
—
—
WRT3*
30000Bh CONFIG6H WRTD WRTB WRTC
—
—
30000Ch CONFIG7L —
—
—
—
EBTR3*
30000Dh CONFIG7H —
EBTRB
—
—
—
Legend: Shaded cells are unimplemented.
* Unimplemented in PIC18FX585 devices; maintain this bit set.
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 357