82845G Datasheet, PDF (99/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.3.14
ROMADR—Video BIOS ROM Base Address Registers (Device 2)
Address Offset:
Default Value:
Access:
Size:
30–33h
00000000h
R/W, RO
32 bits
The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to zeros.
3.5.3.15
Bit
Description
31:18
17:11
10:1
0
ROM Base Address—RO. Hardwired to zeros.
Address Mask—RO. Hardwired to zeros to indicate 256-KB address range.
Reserved. Hardwired to zeros.
ROM BIOS Enable—RO. Hardwired to 0 to indicate that the ROM is not accessible.
CAPPOINT—Capabilities Pointer Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
34h
D0h
RO
8 bits
3.5.3.16
Bit
Description
7:0
Capabilities Pointer Value. This field contains an offset into the function’s PCI Configuration Space
for the first item in the New Capabilities Linked List, the ACPI registers at address D0h.
INTRLINE—Interrupt Line Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Ch
00h
R/W
8 bits
Bit
Description
Interrupt Connection. This field is used to communicate interrupt line routing information. POST
software writes the routing information into this register as it initializes and configures the system.
7:0
The value in this register indicates which input of the system interrupt controller that the device’s
interrupt pin is connected to. This register is needed for Plug N Play software.
Settings of this register field has no effect on GMCH operation as there is no hardware functionality
associated with this register, other than the hardware implementation of the R/W register itself.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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