82845G Datasheet, PDF (38/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Signal Description
2.10 Functional Straps
Signal Name
PSBSEL
MEMSEL
Type
I
I
Description
PSB Frequency Select: The PSBSEL is tied to the external BSEL resistor-divider
circuitry. The value of the PSBSEL pin reflects the PSB frequency. The PSB runs at
400 MHz when PSBSEL is a 0 and runs at 533 MHz when PSBSEL is a 1.
Memory Configuration Select: This pin selects the SDR or DDR board
configuration. The pin should be unconnected for DDR configuration. For SDR
configuration, a pull-down resistor is required. Refer to the Intel^® Pentium^® 4
Processor in 478-Pin Package and Intel^® 845G/845GL/845GV Chipset Platform
Design Guide for details.
2.11 GMCH Sequencing Requirements
Power Plane and Sequencing Requirements:
• Clock Valid Timing:
• GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK.
• HCLKN/HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#.
• There is no DREFCLK timing requirements relative to reset.
Figure 2-2. Intel^® GMCH System Clock and Reset Requirements
POWER
PWROK
RSTIN#
GCLKIN
HCLKN/HCLKP
~100 ms
10 µs
min
~1 ms
valid
10 µs
min
valid
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet