82845G Datasheet, PDF (110/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Functional Description
Table 4-5. Address Translation and Decoding
1 Meg
12 R
64 x 16
32 x 8 o 24 11 12 x[26] 15 14 13 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
2 Meg
12 R
64 x 8
64 x 9 o 25 13 12 x[26] 15 14 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
2 Meg
12 R
128 x 16
64 x 9 o 25 13 12 x[26] 15 14 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
4 Meg
13
256 x 16
128 x 9
x 4 bks
x2
R
o 26 13 12 26
w
15 14 25 24 23 22 21 20 19 18 17 16
4 Meg
12 R
128 x 8
128 x 10 o 26 14 13 x[27] 15 26 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
8 Meg
13 R
256 x 8
256 x 10 o 27 14 13 27
x 4 bks
x2 w
15 26 25 24 23 22 21 20 19 18 17 16
4.2.5
DRAM Performance Description
The overall memory performance is controlled by the DRAM timing register, pipelining depth used
in the GMCH, memory speed grade, and the type of SDRAM used in the system. In addition, the
exact performance in a system is also dependent on the total memory supported, external buffering,
and memory array layout. The most important contribution to overall performance by the system
memory controller is to minimize the latency required to initiate and complete requests to memory,
and to support the highest possible bandwidth (full streaming, quick turnarounds). One measure of
performance is the total flight time to complete a cache line request. A true discussion of
performance involves the entire chipset, not just the system memory controller.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet