82845G Datasheet, PDF (100/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.3.17
INTRPIN—Interrupt Pin Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Dh
01h
RO
8 bits
3.5.3.18
Bit
Description
7:0
Interrupt Pin. As a single function device, the IGD specifies INTA# as its interrupt pin.
01h=INTA#.
MINGNT—Minimum Grant Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
RO
8 bits
3.5.3.19
Bit
Description
7:0
Minimum Grant Value. The IGD does not burst as a PCI compliant master.
Bits[7:0]=00h.
MAXLAT—Maximum Latency Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
3Fh
00h
RO
8 bits
3.5.3.20
Bit
Description
7:0
Maximum Latency Value. Bits[7:0]=00h. The IGD has no specific requirements for how often it
needs to access the PCI bus.
PMCAPID—Power Management Capabilities ID Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
D0h−D1h
0001h
RO
16 bits
Bit
Description
15:8
NEXT_PTR. This contains a pointer to next item in capabilities list. This is the final capability in the
list and must be set to 00h.
7:0 CAP_ID. SIG defines this ID is 01h for power management.
100
Intel^® 82845G/82845GL/82845GV GMCH Datasheet