82845G Datasheet, PDF (117/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Functional Description
Table 4-8. PCI Commands Supported by GMCH When Acting As an AGP/PCI_B Initiator
(Sheet 2 of 2)
Source Bus
Command
Other Encoded Information
Source Bus: Host
EA Memory Access
Address ≥ 4 GB
Source Bus: Hub Interface
Memory Write
-
GMCH Host Bridge
Corresponding
PCI_B Command
GC/BE[3:0]#
Encoding
None
Memory Write
N/A
0111
NOTES:
1. Processor to AGP/PCI_B bus can result in deadlocks. Locked access to AGP/PCI_B bus is strongly
discouraged.
2. N/A refers to a function that is not applicable, Not Supported refers to a function that is available but
specifically not implemented on the GMCH
As an initiator of AGP/PCI_B cycle, the GMCH only supports the following transactions:
• Memory Read: All processor to AGP/PCI_B reads will use the memory read command.
• Memory Write: The GMCH initiates AGP/PCI_B cycles on behalf of the processor or hub
interface. The GMCH does not issue memory write and invalidate as an initiator. The GMCH
does not support write merging or write collapsing. The GMCH combines processor-to-PCI
writes (DWord or QWord) to provide bursting on the AGP/PCI_B bus. The GMCH allows
non-snoopable write transactions from hub interface to the AGP/PCI_B bus.
• I/O Read and Write: I/O read and write from the processor are sent to the AGP/PCI_B bus.
I/O base and limit address range for PCI_B bus are programmed in AGP/PCI_B configuration
registers. All other accesses that do not correspond to this programmed address range are
forwarded to the hub interface.
• Exclusive Access: The GMCH does not issue a locked cycle on AGP/PCI_B bus on the behalf
of either the processor or the hub interface. The hub interface and processor locked
transactions to AGP/PCI_B are initiated as unlocked transactions by the GMCH on the AGP/
PCI_B bus.
4.3.2.2
GMCH Retry/Disconnect Conditions
The GMCH generates retry/disconnect according to the Accelerated Graphics Port Interface
Specification, Revision 2.0 rules when being accessed as a target from the AGP interface (using
PCI semantics).
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
117