82845G Datasheet, PDF (98/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.3.11
MMADR—Memory Mapped Range Address Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
14– 17h
00000000h
R/W, RO
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
3.5.3.12
Bit
31:19
18:4
3
2:1
0
Description
Memory Base Address— R/W. Set by the operating system. These bits correspond to address
signals [31:19].
Address Mask— RO. Hardwired to zeros to indicate 512-KB address range.
Prefetchable Memory— RO. Hardwired to 0 to prevent prefetching.
Memory Type— RO. Hardwired to zeros to indicate 32-bit address.
Memory / IO Space— RO. Hardwired to 0 to indicate memory space.
SVID2—Subsystem Vendor Identification Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
2C– 2Dh
0000h
R/WO
16 bits
3.5.3.13
Bit
Description
Subsystem Vendor ID. This value is used to identify the vendor of the subsystem. This register
15:0 should be programmed by BIOS during boot-up. Once written, this register becomes read only. This
register can only be cleared by a Reset.
SID2—Subsystem Identification Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
2E– 2Fh
0000h
R/WO
16 bits
Bit
Description
Subsystem Identification. This value is used to identify a particular subsystem. This field should be
15:0 programmed by BIOS during boot-up. Once written, this register becomes read only. This register
can only be cleared by a Reset.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet