82845G Datasheet, PDF (45/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
have a Bus Number that matches the Secondary Bus Number of the GMCH’s “virtual” Host-to-
PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the PCI_B/AGP
interface. The GMCH will decode the Device Number field [15:11] and assert the appropriate
GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration
mechanism. The remaining address bits will be mapped as described in Figure 3-2.
Figure 3-2. Configuration Mechanism Type 0 Configuration Address to PCI Address Mapping
CONFIG_ADDRESS
31
24 23
16 15 14
11 10
87
210
1
Reserved
Bus Number
Device Number Function No.
Register Number
xx
31
24 23
16 15
11 10
87
210
IDSEL
Reserved = 0
Function No.
Register Number
00
AGP GAD[31:0] Address
AGP/PCI_B Type 0 Configuration Cycle
Config Address
AD[15:11]
00000
00001
00010
00011
00100
00101
00110
00111
AGP GAD[31:16] IDSEL
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
Config Address
AD[15:11]
01000
01001
01010
01011
01100
01101
01110
01111
1xxxx
AGP GAD[31:16] IDSEL
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
NOTE: If the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number
register, and less than or equal to the value programmed into the Subordinate Bus Number register the
configuration cycle is targeting a PCI bus downstream of the targeted interface. The GMCH will
generate a Type 1 PCI configuration cycle on PCI_B/AGP. The address bits will be mapped as
described in Figure 3-3.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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