82845G Datasheet, PDF (52/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.4
PCISTS—PCI Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
06–07h
0090h
RO, R/WC
16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. Bit 14 is read/write clear. All other bits are Read Only. Since GMCH Device 0 does not
physically reside on PCI_A, many of the bits are not implemented.
Bit
Description
15 Detected Parity Error (DPE)—RO. Hardwired to 0. Not implemented.
Signaled System Error (SSE)—R/WC.
0 = SERR message not generated for Device 0 SERR condition.
1 = GMCH Device 0 generated an SERR message over the hub interface for any enabled Device 0
14
error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD registers.
Device 0 error flags are read/reset from the PCISTS or ERRSTS registers. Software sets SSE
to 0 by writing a 1 to this bit.
NOTE: Software clears this bit by writing a 1 to it.
13
Received Master Abort Status (RMAS)—RO. This bit is set when the GMCH generates a hub
interface request that receives a Master Abort completion packet or Master Abort Special Cycle.
12
Received Target Abort Status (RTAS)—RO. This bit is set when the GMCH generates a hub
interface request that receives a Target Abort completion packet or Target Abort Special Cycle.
11
Signaled Target Abort Status (STAS)—RO. Hardwired to 0. Not implemented. The GMCH will not
generate a Target Abort HI completion packet or Special Cycle.
DEVSEL Timing (DEVT)—RO. Hardwired to 00. Device 0 does not physically connect to PCI_A.
10:9 These bits are set to “00” (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by
the GMCH.
8
Master Data Parity Error Detected (DPD)—RO. Hardwired to 0. PERR signaling and messaging
are not implemented by the GMCH.
Fast Back-to-Back (FB2B)—RO. Hardwired to 1. Device 0 does not physically connect to PCI_A.
7 This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_A is
not limited by the GMCH.
6:5 Reserved.
Capability List (CLIST)—RO. Hardwired to 1. This indicates to the configuration software that this
4
device/function implements a list of new capabilities. A list of new capabilities is accessed via
CAPPTR register (offset 34h). The CAPPTR register contains an offset pointing to the start address
within configuration space of this device where the AGP Capability standard register resides.
3:0 Reserved.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet