82845G Datasheet, PDF (67/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.21
FDHC—Fixed SDRAM Hole Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
97h
00h
R/W, RO
8 bits
This 8-bit register controls a fixed SDRAM hole from 15 MB–16 MB.
3.5.1.22
Bit
Description
Hole Enable (HEN). This field enables a memory hole in SDRAM space. The SDRAM that lies
“behind” this space is not remapped.
7
0 = No memory hole
1 = Memory hole from 15 MB to 16 MB.
6:0 Reserved.
SMRAM—System Management RAM Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
9Dh
02h
R/W, RO, L
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The open, close, and lock bits function only when G_SMRAME bit is set to a 1. Also, the
open bit must be reset before the lock bit is set.
Bit
Description
7 Reserved.
SMM Space Open (D_OPEN)—R/W, L. When D_OPEN=1 and D_LCK=0, the SMM space SDRAM
6 is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.
SMM Space Closed (D_CLS)—R/W. When D_CLS = 1, SMM space SDRAM is not accessible to
data references, even if SMM decode is active. Code references may still access SMM space
5 SDRAM. This will allow SMM software to reference through SMM space to update the display even
when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1
are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM space.
SMM Space Locked (D_LCK)—R/W, L. When D_LCK is set to 1, D_OPEN is reset to 0; D_LCK,
D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. D_LCK
can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The
4 combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to “lock down” SMM space in the
future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if
the program has knowledge of the D_OPEN function.
Global SMRAM Enable (G_SMRARE)—R/W, L. If set to a 1, Compatible SMRAM functions are
3
enabled, providing 128 KB of SDRAM accessible at the A0000h address while in SMM (ADS# with
SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to Chapter 5 for
more details. Once D_LCK is set, this bit becomes read only.
Compatible SMM Space Base Segment (C_BASE_SEG)—R/W, L. This field indicates the location
2:0
of SMM space. SMM SDRAM is not remapped. It is simply made visible if the conditions are right to
access SMM space, otherwise the access is forwarded to the hub interface. Since the GMCH
supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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