82845G Datasheet, PDF (17/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Introduction
1.4
1.4.1
1.4.2
1.4.3
Intel^® 82845G GMCH Overview
The GMCH provides the processor interface, SDRAM interface, AGP interface, hub interface, and
integrated graphics with several display interfaces.
Host Interface
The GMCH supports a single mPGA 478 processor with PSB frequencies of 400 MHz (100 MHz
HCLK) / 533 MHz (133 MHz HCLK) and it also supports Hyper-Threading Technology. The
GMCH uses a scalable PSB VTT between 1.15 V and 1.75 V and on-die termination.
The GMCH supports 32-bit host addressing (decoding up to 4 GB of the processor’s memory
address space). Host-initiated I/O cycles are decoded to the AGP/PCI_B, hub interface or GMCH
configuration space. Host-initiated memory cycles are decoded to AGP/PCI_B, the hub interface,
or system memory. All memory accesses from the host interface that hit the graphics aperture are
translated using an AGP address translation table. AGP/PCI_B device accesses to non-cacheable
system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_B
using PCI semantics and from the hub interface to system memory are snooped on the host bus.
System Memory Interface
The GMCH supports either a single channel of SDR (Single Data Rate) SDRAM or DDR (Double
Data Rate) SDRAM. The channel can be either DDR 200/266 SDRAM memory or SDR PC133
SDRAM memory, with a 64-bit wide interface. Two DIMMs are supported in each configuration.
The system memory signals for DDR are multiplexed with signals for SDR. When DDR mode is
selected, the memory buffers support the SSTL_2 signal interface. When SDR mode is selected,
the memory buffers support the LVTTL signal interface. The memory controller interface is fully
configurable through a set of control registers.
The memory interface supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb (megabit) SDRAM
technologies. Using 512-Mb SDRAM technology, up to 2 GB of DDR or SDR memory is
supported. The memory interface supports variable page sizes of 2 KB, 4 KB, 8 KB, and 16 KB.
Page size is individually selected by row, and up to 16 simultaneously open pages (four per row)
can be supported. Both DDR and SDR configurations support data masking, but do not support
ECC. The GMCH supports industry standard DIMMs. Only DIMM configurations defined in the
JEDEC DDR Specifications are supported for DDR. The DDR configuration supports non-
inverting selective command-per-clock (selective CPC) accesses.
Hub Interface
The hub interface connects the GMCH to the ICH4. Most communication between the GMCH and
the ICH4 occurs over this interface. The hub interface runs at 66 MHz/266 MB/s and is powered
with 1.5 V.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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