82845G Datasheet, PDF (64/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.20
Bit
Description
3:1 Intel Reserved.
DRAM Type (DT)—RO. This bit indicates SDRAM type.
0
0 = Single Data Rate (SDR) SDRAM
1 = Double Data Rate (DDR) SDRAM
PAM[0:6]—Programmable Attribute Map Registers (Device 0)
Address Offset:
Default Value:
Attribute:
Size:
90–96h
00h
R/W, RO
8 bits
The GMCH allows programmable memory attributes on 13 Legacy memory segments of various
sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM) Registers
are used to support these features. Cacheability of these areas is controlled via the MTRR registers
in the processor. Two bits are used to specify memory attributes for each memory segment. These
bits apply to host initiator only access to the PAM areas. The GMCH forwards to main memory for
any AGP, PCI or hub interface initiated accesses to the PAM areas. These attributes are:
• RE - Read Enable. When RE = 1, the host read accesses to the corresponding memory
segment are claimed by the GMCH and directed to main memory. Conversely, when RE = 0,
the host read accesses are directed to PCI_A.
• WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the GMCH and directed to main memory. Conversely, when WE = 0,
the host write accesses are directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and defined in the following
table.
Bits [7, 3]
Reserved
X
X
X
X
Bits [6, 2]
Reserved
X
X
X
X
Bits [5, 1]
WE
0
0
1
1
Bits [4, 0]
RE
0
1
0
1
Description
Disabled DRAM is disabled and all accesses are
directed to the Hub Interface A. The MCH does not
respond as a PCI target for any read or write
access to this area.
Read Only. Reads are forwarded to DRAM and
writes are forwarded to the Hub Interface A for
termination. This write protects the corresponding
memory segment. The MCH will respond as an
AGP or the Hub Interface A target for read
accesses but not for any write accesses.
Write Only. Writes are forwarded to DRAM and
reads are forwarded to the Hub Interface for
termination. The MCH will respond as an AGP or
Hub Interface A target for write accesses but not
for any read accesses.
Read/Write. This is the normal operating mode of
main memory. Both read and write cycles from the
host are claimed by the MCH and forwarded to
DRAM. The MCH will respond as an AGP or the
Hub Interface A target for both read and write
accesses.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet