82845G Datasheet, PDF (58/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.15
GC—Graphics Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
52h
0000_1000b
R/W
8 bits
Bit
Description
7 Reserved. Default = 0
Graphics Mode Select (GMS)—R/W. This field is used to select the amount of Main Memory that is
pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes.
These 3 bits are valid only when Internal graphics is enabled.
000 = No memory pre-allocated. Default
001 = Reserved.
6:4 ^{010 = DVMT (UMA) mode, 512 KB of memory pre-allocated for frame buffer.}
011 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer.
100 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer.
All other combinations reserved.
NOTE: These register bits are locked and become read only when the D_LCK bit in the SMRAM
register is set.
Integrated Graphics Disable (IGDIS)—R/W¹.
0 = Enable (Internal Graphics is enabled). The GMCH’s Device 1 is disabled such that all
configuration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field in
the CAPREG register (Dev 0, Offset E4h) will be RO at 00h.
1 = Disable (Internal Graphics is disabled and AGP Graphics is enabled). (default). The GMCH’s
3
Device 2 is disabled such that all configuration cycles to Device 2 flow through to the hub
interface.
NOTE:
1. When writing a new value to this bit, a warm reset through the ICH4 must be executed before the
bit becomes effective. This must be enforced by BIOS. However, changing this bit in software
requires a “warm reset”.
Internal Graphics IO Aliasing Enable (IGIOALIASEN)—R/W.
0 = Disable (Default). the IGD observes address bits 15:10 (must be all zeros) while decoding VGA
I/O transactions. No VGA IO alias addresses are claimed by the IGD. I/O addresses not
2
claimed by the IGD (excluding CONFIG_ADDRESS and CONFIG_DATA) subtractively decode
to the hub interface.
1 = Enable. The IGD ignores PSB address bits 15:10 (address bits 9:3 are always decoded) when
decoding VGA IO transactions. Subject to other qualifications documented elsewhere, VGA I/O
alias addresses are claimed by the IGD.
IGD VGA Disable (IVD)—R/W.
0 = Enable (Default). IGD claims VGA memory and IO cycles and the Sub-Class Code within
1
Device 2 Class Code register is 00.
1 = Disable. The IGD does Not claim VGA cycles (Mem and IO), and the Sub-Class Code field
within Device 2 Class Code register is 80h.
Graphics Memory Size (GMEMS)—R/W. This bit controls GMADR register in Device 2
0 0 = 128 MB (Default)
1 = 64 MB
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet