82845G Datasheet, PDF (62/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.18
DRT—DRAM Timing Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
78–7Bh
00000000h
Read/Write
32 bits
This register controls the timing of the DRAM controller.
Bit
31:18
17:15
14:12
11
10:9
8:7
6:5
4
3:2
1:0
Description
Intel Reserved.
DRAM Idle Timer. This field determines the number of clocks the SDRAM controller will remain in
the idle state before it begins pre-charging all pages.
000 = Infinite
001 = 0
010 = 8 DRAM clocks
011 = 16 DRAM clocks
100 = 64 DRAM clocks
Others = reserved
Intel Reserved.
Activate to Precharge Delay (tRAS), MAX. This bit controls the maximum number of clocks that a
DRAM (SDR or DDR) bank can remain open. After this time period, the DRAM controller will
guarantee to pre-charge the bank. Note that this time period may or may not be set to overlap with
time period that requires a refresh to happen.
The DRAM controller incudes a separate tRAS-MAX counter for every supported bank. With a
maximum of four row and four banks per row, there are 16 counters.
0 = 120 µs
1 = Reserved.
Activate to Precharge delay (tRAS), MIN. This bit controls the number of DRAM clocks for tRAS
minimum.
00 = 8 Clocks
01 = 7 Clocks
10 = 6 Clocks
11 = 5 Clocks
Intel Reserved.
CAS# Latency (tCL).
Encoding SDR CL
00
Reserved
01
3
10
2
11
Reserved
DDR CL
2.5
2
Reserved
Reserved
Intel Reserved.
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
01 = 3 DRAM Clocks
10 = 2 DRAM Clocks
11 = Reserved
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
00 = Intel Reserved
01 = 3 DRAM Clocks
10 = 2 DRAM Clocks
11 = Reserved
62
Intel^® 82845G/82845GL/82845GV GMCH Datasheet