82845G Datasheet, PDF (26/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Signal Description
2.2.2
SDR SDRAM Interface
The SDR interface signals are multiplexed with the DDR signals. At power up the functional strap
setting on MEMSEL determines whether the memory interface is set up for DDR or SDR. The
DDR-to-SDR signal mapping is provided in Table 2-1.
Signal Name
SCK_[7:0]
SCS_[7:0]#
SMAA_[12:0]
SBA_[1:0]
SRAS#
SCAS#
SWE#
SDQ_[63:0]
SDM_[7:0]
SCKE_[3:0]
SRDCLK_OUT
SRDCLK_IN
Type
Description
O LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
I/O
LVTTL
O LVTTL
O
LVTTL
O
LVTTL
I
LVTTL
SDR System Memory Clock: These signals provide the 133 MHz SDRAM
clocks for the DIMMs. Note that there are two SCK per SDRAM row.
Chip Select: These pins select the particular SDRAM components during the
active state. Note that there are two SCS# per SDRAM row. These signals can
be toggled on every rising system memory clock edge.
Memory Address: These signals provide the multiplexed row and column
address to SDRAM.
Bank Select (Bank Address): The bank select signals and memory address
signals combine to address every possible location within an SDRAM device.
Row Address Strobe: SRAS# is used with SCAS# and SWE# (along with
SCS#) to define the SDRAM commands.
Column Address Strobe: SCAS# is used with SRAS# and SWE# (along with
SCS#) to define the SDRAM commands.
Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#) to
define the SDRAM commands.
Data Lines: SDQ_[63:0] interface to the SDRAM data bus.
Data Mask: When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SDM for every eight data lines.
Clock Enable: These signals are used for placing all SDRAM rows into and out
of self-refresh during Suspend-to-RAM. SCKE is also used to dynamically
power down inactive SDRAM rows. There is one SCKE per SDRAM row.
Read Clock Out: Feedback testpoint signal used to emulate source-synch
clocking for reads. This pin should be connect to SRDCLK_IN through an un-
populated backside resistor site.
Read Clock Input: Feedback testpoint signal used to emulate source-synch
clocking for reads.
Table 2-1. DDR-to-SDR Signal Mapping (Sheet 1 of 3)
DDR Ball Name SDR Ball Name Ball #
DDR Ball Name SDR Ball Name
SMXRCOMP
SMYRCOMP
SDQ_59
SCKE_2
SMAA_9
SMAB_5
SMAA_3
SCMDCLK_0#
SRCVEN_OUT#
SMAA_10
SMXRCOMP
SMYRCOMP
SDQ_63
SWE#
SCS_4#
SCS_0#
SMAA_0
SMAA_5
SRCVEN_OUT#
SBA_0
AF10
AJ34
AJ36
AK14
AK16
AK18
AK20
AK22
AK24
AK26
SWE#
SDQ_5
SDQ_43
SCS_1#
SDQ_52
SCMDCLK_5
SDQ_54
SDQ_51
SDQ_60
SDM_0
SCKE_3
SDQ_1
SDQ_54
SCS_6#
SDQ_24
SCMDCLK_2
SDQ_57
SDQ_27
SDQ_59
SDQ_2
Ball #
AP29
AP3
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP4
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet