82845G Datasheet, PDF (173/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Testability
Testability
8
In the GMCH, testability for Automated Test Equipment (ATE) board level testing has been
implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin
connected to it.
8.1
XOR Test Mode Initialization
XOR test mode can be entered by driving GSBA[6] and GSBA[7] low, and TESTIN# low, and
PWROK low, and RSTIN# low, then drive PWROK high, then RSTIN# high. XOR test mode via
TESTIN# does not require a clock.
8.2
XOR Chain Definition
The GMCH has nine XOR chains. The XOR chain outputs are driven out on the DDR output pins
(see Table 8-1).
Table 8-1. XOR Chain Output Pins
XOR Chain
0
1
2
3
4
5
6
7
8
DDR Output Pin
Channel A
SMAA_0
SMAA_1
SMAA_2
SMAA_3
SMAA_4
SMAA_5
SMAA_6
SRAS#
SBA_0
DDR Output Pin
Channel B
SMAA_7
SMAA_8
SMAA_9
SMAA_10
SMAA_11
SMAA_12
SWE#
SCAS#
SBA_1
Table 8-2, Table 8-3, and Table 8-4 show the XOR chain pin mappings and their monitors for the
GMCH.
Note:
Only AGP differential STROBEs are on different chains but in the same channel group. The rest of
the interfaces’ STROBEs are on the same chain, since they do not require opposite polarity at all
the times. All XOR chains can be run in parallel except chains with AGP strobes. Thus, chain 0 and
chain 1 cannot be run in parallel; similarly chain 2 and chain 3.
Note: The Channel A and Channel B output pins for each Chain show the same output.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
173