82845G Datasheet, PDF (184/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Intel^® 82845GL/82845GV GMCH
9.4.1.2
ATTBASE — Aperture Translation Table Register (Device 0)
Address Offset
Size:
B8–BBh
32 bits
AMTT — AGP MTT Control Register (Device 0)
Address Offset
Size:
BC–BFh
8 bits
LPTT — AGP Low Priority Transaction Timer Register (Device 0)
Address Offset
Size:
BDh
8 bits
Device 0 Register Bit Differences
The registers described in this section are in both the 82845G and 82845GL/82845GV. However,
some of the register bits have different functions/operations between the components. Only the bits
that are different are shown in this section. Thus, the bit descriptions shown in this section only
apply to the 82845GL or 82845GV. The remaining register bits are the same for all three
components and are described in Chapter 3.
GC—Graphics Control Register (Device 0)
Address Offset
Default Value
Access
Size:
52h
0000_0000b
RO
8 bits
Bits
Description
Integrated Graphics Disable (IGDIS). The GMCH’s Device 1 is disabled such that all
configuration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field in
3
the CAPREG register (Device 0, Offset E4h) is RO at 00h. This enables internal graphics
capability.
0 = Enable. Internal Graphics is enabled (default)
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet