82845G Datasheet, PDF (185/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Intel^® 82845GL/82845GV GMCH
GMCHCFG—GMCH Configuration Register (Device 0)
Address Offset
Default Value
Access
Size:
C6–C7h
0C01h
R/W, RO
16 bits
Bits
Description
12
(82845GL
Only)
Core/PSB Frequency Select (PSBFREQ)—RO. The default value of this bit is set by the strap
assigned to pin PSBSEL and is latched at the rising edge of PWROK.
0 = PSB frequency is 400 MHz (PSBSEL sampled high on PWROK assertion)
1 = Indicates a processor running 533 MHz on the board. For the 82845GL, the board will not
boot.
AGP Mode (AGP/DVO#)—RO. This bit reflects the ADD_DETECT strap value. This strap bit
determines the function of the AGP I/O signal.
0 = 2xDVO
1 = no DVO mode, internal graphics only.
3
When the strap is sampled low, this bit will be a 0 and DVO mode will be selected. When the
strap is sampled high, this bit will be a 1 and DVO mode will not be selected, and the internal
graphics device would be running.
Note that when this bit is set to 0 (DVO mode), Device 1 is disabled (configuration cycles fall-
through to the hub interface) and the Next Pointer field in CAPREG will be hardwired to zeros.
ERRSTS—Error Status Register (Device 0)
Address Offset
Default Value
Access
Size:
C8–C9h
0000h
R/WC
16 bits
Bits
4:0
Intel Reserved
Description
ERRCMD—Error Command Register (Device 0)
Address Offset
Default Value
Access
Size:
CA–CBh
0000h
RO, R/W
16 bits
Bits
4:0
Intel Reserved
Description
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
185