82845G Datasheet, PDF (78/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.2 Host-to-AGP Bridge Registers (Device 1)
The host-to-AGP Bridge (virtual PCI-to-PCI) registers are in Device 1. This section contains the
PCI configuration registers listed in order of ascending offset address. Table 3-3 provides the
register address map for this device.
Table 3-3. Host-to-AGP Register Address Map (Device 1)
Address
Offset
00–01h
02–03h
04–05h
06–07h
Symbol
VID1
DID1
PCICMD1
PCISTS1
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
08h
RID1
Revision Identification
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0F–17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–3Dh
3Eh
40h
41–FFh
—
SUBC1
BCC1
—
MLT1
HDR1
—
PBUSN1
SBUSN1
SUBUSN1
SMLT1
IOBASE1
IOLIMIT1
SSTS1
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
—
BCTRL1
ERRCMD1
—
Intel Reserved
Sub-Class Code
Base Class Code
Intel Reserved
Master Latency Timer
Header Type
Intel Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Bus Master Latency Timer
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Limit
Address
Prefetchable Memory Limit Address
Intel Reserved
Bridge Control
Error Command
Intel Reserved
Default Value
Access
8086h
2561h
0000h
00A0h
see register
description
—
04h
06h
—
00h
01h
—
00h
00h
00h
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
—
00h
00h
—
RO
RO
RO, R/W
RO, R/WC
RO
—
RO
RO
—
RO, R/W
RO
—
RO
R/W
R/W
RO, R/W
RO, R/W
RO, R/W
RO, R/WC
RO, R/W
RO, R/W
RO, R/W
RO, R/W
—
RO, R/W
RO, R/W
—
78
Intel^® 82845G/82845GL/82845GV GMCH Datasheet