82845G Datasheet, PDF (14/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Introduction
1.2
Term
Graphics Core
HI
Host
Intel^® ICH4
IGD
LVTTL
Primary PCI
PSB
Scalable Bus
SDR
SDRAM
Secondary PCI
SSTL_2
Description
The internal graphics related logic in the GMCH. Also known as the Integrated Graphics
Device (IGD).
Hub Interface. The proprietary hub interconnect that ties the GMCH to the ICH4. In this
document HI cycles originating from or destined for the primary PCI interface on the ICH4
are generally referred to as HI/PCI or simply HI cycles.
This term is used synonymously with processor or CPU.
Fourth generation I/O Controller Hub component.
Integrated Graphics Device. Graphics device integrated into the GMCH.
Low Voltage TTL 3.3 V (SDR).
The physical PCI bus that is driven directly by the ICH4 component. Communication
between the PCI and the GMCH occurs over the hub interface. Note that even though the
Primary PCI bus is referred to as PCI, it is not PCI Bus #0 from a configuration standpoint.
Processor System Bus. This is the bus between the GMCH and processor (also referred
to as the Host, FSB, or processor bus).
Processor-to-GMCH interface. The Compatible Mode of the Scalable Bus is the P6 bus.
The Enhanced Mode of the Scalable Bus is the P6 Bus plus enhancements primarily
consisting of source synchronous transfers for address and data, and PSB interrupt
delivery. The Intel^® Pentium 4 processor implements a subset of Enhanced Mode.
Single Data Rate SDRAM.
Synchronous Dynamic Random Access Memory.
The physical PCI interface that is a subset of the AGP bus driven directly by the GMCH. It
supports a subset of 32-bit, 66 MHz PCI Local Bus Specification, Revision 2.1-compliant
components, but only at 1.5 V (not 3.3 V or 5 V).
Stub Series Terminated Logic for 2.5 V (DDR).
Related Documents
Document
Intel^® Pentium^® 4 Processor in 478-Pin Package and Intel^® 845G/845GL/
82845GV Chipset Platform Design Guide
Intel^® 845G/845GL/845GV Chipset Thermal Design Guide
Intel^® 82801DB I/O Controller Hub 4 (ICH4) Datasheet
Intel^® Pentium^® 4 Processor in the 478-Pin Package Datasheet
JEDEC Double Data Rate (DDR) SDRAM Specification
Intel^® PC SDRAM Specification
Accelerated Graphics Port Interface Specification, Revision 2.0
Digital Visual Interface (DVI) Specification, Revision 1.0
Document Number/ Location
298654
298655
290744
249887
www.jedec.org
http://developer.intel.com/
technology/memory/pcsdram/
spec/index.htm
http://www.intel.com/technology/
agp/agp_index.htm
NOTE: For additional related documents, refer to the Intel^® Pentium^® 4 Processor in 478-Pin Package and
Intel^® 845G/845GL/845GV Chipset Platform Design Guide.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet