82845G Datasheet, PDF (73/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.1.32
GMCHCFG—GMCH Configuration Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
C6–C7h
0C01h
R/W, RO
16 bits
Bit
15:13
12
11:10
9:6
5
4
3
RO
2
1:0
Description
Intel Reserved.
Core/PSB Frequency Select (PSBFREQ)—RO. The default value of this bit is set by the strap
assigned to pin PSBSEL and is latched at the rising edge of PWROK.
0 = PSB frequency is 400 MHz (PSBSEL sampled low on PWROK assertion)
1 = PSB frequency is 533 MHz (PSBSEL sampled high on PWROK assertion)
System Memory Frequency Select (SMFREQ)—R/W¹.
00 = Intel Reserved
01 = Intel Reserved
10 = System Memory frequency is set to 133 MHz (SDR133, DDR266)
11 = System Memory frequency is set to 100 MHz (DDR200) (Default)
NOTE:
1. When writing a new value to this bit, a warm reset through the Intel^® ICH4 must be executed
before the bit becomes effective. This must be enforced by BIOS/SW. However, changing this bit
in SW requires a “warm reset”
Intel Reserved.
MDA Present (MDAP). This bit works with the VGA enable bits in the BCTRL1 register of Device 1
to control the routing of processor initiated transactions targeting MDA compatible I/O and memory
address ranges. This bit should not be set if Device 1's VGA enable bit is not set. If Device 1's VGA
enable bit is set, then accesses to I/O address range x3BCh-x3BFh are forwarded to the hub
interface. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are
treated just like any other I/O accesses. That is, the cycles are forwarded to AGP if the address is
within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are
forwarded to the hub interface. MDA resources are:
Memory: 0B0000h–0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to
hub interface even if the reference includes I/O locations not listed above.
Refer to the Chapter 5 for further information.
Intel Reserved.
AGP Mode (AGP/DVO#)—RO. This bit is Read Only and reflects the ADD_DETECT strap value.
This strap bit determines the function of the AGP I/O signal.
0 = 2xDVO
1 = AGP
When the strap is sampled low, this bit will be a 0 and DVO mode will be selected. When the strap is
sampled high, this bit will be a 1 and AGP mode will be selected.
Note that when this bit is set to 0 (DVO mode), Device 1 is disabled (configuration cycles fall-through
to HI) and the Next Pointer field in CAPREG will be hardwired to zeros.
PSB IOQ Depth (IOQD)—RO. This bit is RO and reflects the HA[7]# strap value. It indicates the
depth of the PSB IOQ.
0 = 1 deep
1 = 12 on the bus, 8 on the GMCH
When the strap is sampled low, this bit will be a 0 and the PSB IOQ depth is set to 1. When the strap
is sampled high, this bit will be a 1 and the PSB IOQ depth is set to the maximum (12 on the bus, 8
on the GMCH).
Intel Reserved.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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