82845G Datasheet, PDF (48/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5
Intel^® GMCH Internal Device Registers
3.5.1
DRAM Controller/Host-Hub Interface Device Registers
(Device 0)
The DRAM controller and host-hub interface registers are in Device 0. This section contains the
PCI configuration registers listed in order of ascending offset address. Table 3-1 provides the
register address map for this device.
Table 3-1. DRAM Controller/Host-Hub Register Address Map (Device 0) (Sheet 1 of 2)
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
09
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–50h
51h
52h
53–5Fh
60–63h
64–6Fh
70–71h
72–77h
78–7Bh
7C–7Fh
80–8Fh
Symbol
VID
DID
PCICMD
PCISTS
RID
—
SUBC
BCC
—
MLT
HDR
—
APBASE
—
SVID
SID
—
CAPPTR
—
AGPM
GC
—
DRB[0:3]
—
DRA[0:3]
—
DRT
DRC
—
Register Name
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification
Intel Reserved
Sub-Class Code
Base Class Code
Intel Reserved
Master Latency Timer
Header Type
Intel Reserved
Aperture Base Configuration
Intel Reserved
Subsystem Vendor Identification
Subsystem Identification
Intel Reserved
Capabilities Pointer
Intel Reserved
AGP Miscellaneous Configuration
Graphics Control
Intel Reserved
DRAM Row Boundary (4 registers)
Intel Reserved
DRAM Row Attribute (4 registers)
Intel Reserved
DRAM Timing Register
DRAM Controller Mode
Intel Reserved
Default Value
8086h
2560h
0006h
0090h
see register
description
—
00h
06h
—
00h
00h
—
00000008h
—
0000h
0000h
—
E4h
—
00h
0000_1000b
—
01h
—
00h
—
00000000h
00000000h
—
Access
RO
RO
RO, R/W
RO, R/WC
RO
—
RO
RO
—
RO
RO
—
RO, R/W
—
R/WO
R/WO
—
RO
—
R/W
R/W
—
RW
—
RW
—
RW
RW, RO
—
48
Intel^® 82845G/82845GL/82845GV GMCH Datasheet