82845G Datasheet, PDF (94/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.3.3
PCICMD2—PCI Command Register (Device 2)
Address Offset:
Default:
Access:
Size:
04h−05h
0000h
RO, R/W
16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back-to-Back (FB2B)—RO. Hardwired to 0. Not Implemented.
SERR# Enable (SERRE)—RO. Hardwired to 0. Not Implemented.
Address/Data Stepping—RO. Hardwired to 0. Not Implemented.
Parity Error Enable (PERRE)—RO. Hardwired to 0. Not Implemented. Since the IGD belongs to
the category of devices that does not corrupt programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues with normal operation.
Video Palette Snooping (VPS)—RO. This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. The IGD does not support
memory write and invalidate commands.
Special Cycle Enable (SCE)—RO. Hardwired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME)—R/W.
0 = Disable IGD bus mastering (default).
1 = Enable the IGD to function as a PCI compliant master.
Memory Access Enable (MAE)—R/W. This bit controls the IGD’s response to memory space
accesses.
0 = Disable (default).
1 = Enable.
I/O Access Enable (IOAE)—R/W. This bit controls the IGD’s response to I/O space accesses.
0 = Disable (default).
1 = Enable.
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet