82845G Datasheet, PDF (85/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Register Description
3.5.2.14
IOBASE1—I/O Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Ch
F0h
RO, R/W
8 bits
This register controls the processor to PCI_B/AGP I/O access routing based on the following
formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
3.5.2.15
Bit
Description
7:4
I/O Address Base (IOBASE). Corresponds to A[15:12] of the I/O addresses passed by bridge 1 to
AGP/PCI_B.
3:0 Reserved.
IOLIMIT1—I/O Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
RO, R/W
8 bits
This register controls the processor to PCI_B/AGP I/O access routing based on the following
formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper four bits are programmable. For the purpose of address decode, address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of
a 4-KB aligned address block.
Bit
Description
7:4
I/O Address Limit (IOLIMIT). This field corresponds to A[15:12] of the I/O address limit of Device 1.
Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B.
3:0 Reserved.
Intel^® 82845G/82845GL/82845GV GMCH Datasheet
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