82845G Datasheet, PDF (24/193 Pages) Intel Corporation – Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)

Signal Description
Signal Name
HDSTB_P[3:0]#
HDSTB_N[3:0]#
HIT#
HITM#
HLOCK#
HREQ_[4:0]#
HTRDY#
RS_[2:0]#
Type
Description
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I
AGTL+
I/O
AGTL+
2X
O
AGTL+
O
AGTL+
Differential Host Data Strobes: HDSTB_P[3:0]# and HDSTB_N[3:0]# are the
differential source synchronous strobes used to transfer HD_[63:0]# and
DINV_[3:0]# at the 4X transfer rate.
Strobe
Data Bits
HDSTB_P3#, HDSTB_N3#
HD_[63:48]#, DINV_3#
HDSTB_P2#, HDSTB_N2#
HD_[47:32]#, DINV_2#
HDSTB_P1#, HDSTB_N1#
HD_[31:16]#, DINV_1#
HDSTB_P0#, HDSTB_N0#
HD_[15:0]#, DINV_0#
Hit: This signal indicates that a caching agent holds an unmodified version of
the requested line. Also, driven in conjunction with HITM# by the target to
extend the snoop window.
Hit Modified: This signal indicates that a caching agent holds a modified
version of the requested line and that this agent assumes responsibility for
providing the line. HITM# is also driven in conjunction with HIT# to extend the
snoop window.
Host Lock: All processor bus cycles sampled with the assertion of HLOCK#
and ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface
or AGP snoopable access to SDRAM are allowed when HLOCK# is asserted
by the processor).
Host Request Command: These signals define the attributes of the request.
HREQ_[4:0]# are transferred at 2X rate. They are asserted by the requesting
agent during both halves of Request Phase. In the first half the signals define
the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second half the signals carry additional information to define the
complete transaction type.
The transactions supported by the GMCH Host Bridge are defined in
Section 4.1.
Host Target Ready: This signal indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Signals: RS_[2:0]# indicate the type of response according to the
encoding below:
000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by GMCH)
100 = Hard Failure (not driven by GMCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response
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Intel^® 82845G/82845GL/82845GV GMCH Datasheet