82551QM Datasheet, PDF (81/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
Table 37. Statistical Counters
ID
Counter
Description
64 Flow Control Transmit Pause
This counter contains the number of Flow Control frames
transmitted by the 82551QM. This count includes both the
Xoff frames transmitted and Xon (PAUSE(0)) frames
transmitted.
68 Flow Control Receive Pause
This counter contains the number of Flow Control frames
received by the 82551QM. This count includes both the Xoff
frames received and Xon [PAUSE(0)] frames received.
This counter contains the number of MAC Control frames
received by the 82551QM that are not Flow Control Pause
72 Flow Control Receive Unsupported frames. These frames are valid MAC control frames that have
the predefined MAC control Type value and a valid address
but has an unsupported opcode.
76 Receive TCO Frames
This counter contains the number of TCO packets received by
the 82551QM.
78 Transmit TCO Frames
This counter contains the number of TCO packets transmitted.
The Statistical Counters are initially set to zero by the 82551QM after reset. They cannot be preset
to anything other than zero. The 82551QM increments the counters by internally reading them,
incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In
addition, the counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
• The 82551QM updates the required counters for each frame. It is possible for more than one
counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 82551QM supports all mandatory and recommend statistics functions through
the status of the receive header and directly through these Statistical Counters.
The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a “snapshot”, in main memory, of the internal 82551QM statistical counters. The
82551QM supports 21 counters. The dump could consist of either 16 or 21 counters, depending on
the status of the Extended Statistics Counters and TCO Statistics configuration bits in the
Configuration command.
10.3
Modem Control/Status Registers
Access to modem based memory or I/O ports are mapped to a modem cycle with the lowest 16
addresses of the PCI address space that is mapped to the modem address bus. This is connected to
FLA3:0.
Datasheet
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