82551QM Datasheet, PDF (23/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
5.2.1.1
To perform these actions, the 82551QM is controlled and examined by the CPU through its control
and status structures and registers. Some of these structures reside in the 82551QM and some
reside in system memory. For access to the 82551QM’s Control/Status Registers (CSR), the
82551QM acts as a slave device. The 82551QM serves as a slave also while the CPU accesses its
128 KB Flash buffer or its EEPROM. When the 82551QM is in modem mode, it also acts as a
slave. Details regarding modem interface are described in Section 5.6, “Parallel Flash/Modem
Interface”.
Section 5.2.1.1 describes the 82551QM slave operation. It is followed by a description of the
82551QM operation as a bus master (initiator) in Section 5.2.1.2.
Bus Slave Operation
The 82551QM serves as a target device in the following cases:
• CPU accesses to the 82551QM System Control Block (SCB) Control/Status Registers (CSR)
• CPU accesses to the EEPROM through its CSR
• CPU accesses to the 82551QM PORT address through the CSR
• CPU accesses to the MDI control register in the CSR
• CPU accesses to the Flash control register in the CSR
• CPU accesses to the 128 KB Flash
The CSR and the 1 MB Flash buffer are considered by the 82551QM as totally separated memory
spaces. The 82551QM provides separate Base Address Registers (BARs) in the configuration
space to distinguish between them. The size of the CSR memory space is 4 KB in the memory
space and 64 bytes in the I/O space. The 82551QM treats accesses to these memory spaces
differently.
5.2.1.1.1 Control/Status Register (CSR) Accesses
The 82551QM supports zero wait state single cycle memory or I/O mapped accesses to its CSR
space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish
these accesses. The 82551QM provides 4 valid KB of CSR space, which include the following
elements:
• System Control Block (SCB) registers
• PORT register
• Flash control register
• EEPROM control register
• MDI control register
• Flow control registers
• CardBus registers
The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing
the Control/Status Registers, the CPU is the initiator and the 82551QM is the target of the
transaction.
Datasheet
17