82551QM Datasheet, PDF (2/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Revision History
Revision
Date
Oct 2001
Dec 2001
Apr 2002
Mar 2003
Jun 2003
Oct 2003
Mar 2004
Oct 2004
Nov 2004
Jan 2005
Apr 2006
Oct 2006
July 2007
Sept 2007
Mar 2008
Nov 2008
Revision
0.6
1.0
2.0
2.1
3.0
3.1
3.11
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
Description
• Removed references to IPSec support and changed description of FLA1/AUXPWR to use a
pull-up resistor if auxiliary power is present, else leave it disconnected.
• Changed description of VCCR to show connecting it directly to main 3.3V supply and reduced
text describing bus operations.
• Reduced PHY functional description to overview level and reorganized manageability section,
adding ASF text. Added 0Fh as Revision ID and added targeted Icc specs.
• Added description for No Connect pins and corrected typographical errors.
Changed document status to Intel Confidential.
• Removed document status and removed references to MDI/MDI-X feature, which is not sup-
ported by the 82551QM
• Added information for the 82551IT.
• Corrected operating temperature range in specifications to 0° to 70° C.
• Added operating temperature reference to Section 1.1
• Removed operating temperature reference to Section 1.1.
• Added references to MDI/MDI-X feature, which is now supported by the 82551QM and
removed information for the 82551IT.
• Updated the section describing “Multiple Priority Transmit Queues”.
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer
0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information.
• Added statement that no changes to existing soldering processes are needed for the 2-layer
0.32 mm wide-trace substrate change in the section describing “Package Information”.
• Added a note for PHY signals RBIAS100 and RBIAS10 to Table 9.
• Changed case temperature specification to “0° C to 85° C”.
• Added Figure 31 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and
metal diameter dimensions.
• Added Section 15 “Reference Schematics”, updated Section 12.1 (changed Tcase to ambient)
and added ordering information to Section 1.4.
• Updated Figures 34 and 35. Added Digital I/O and Crystal Input One (X1) Characteristics
(Tables 70 and 71). Updated Section 5.8.4.
• Updated Figure 35: changed TEST pull down resistor value (62 K to 1 K).
• Updated Table 9 (X1 and X2 pin descriptions).
• Updated Tables 70 and 71 (Digital I/O and crystal input one (X1) characteristics).
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Datasheet