82551QM Datasheet, PDF (73/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
Table 27. System Control Block Status Word
Bits
Name
Description
8
FCP
Flow Control Pause. The FCP bit is used as the flow control pause bit.
7:6
CUS
Command Unit Status. The CUS field contains the status of the Command
Unit.
5:2
RUS
Receive Unit Status. The RUS field contains the status of the Receive Unit.
1:0
Reserved
These bits are reserved and should be set to 0b.
10.1.2
System Control Block Command Word
Commands for the 82551QM’s Command and Receive units are placed in this register by the CPU.
Table 28. System Control Block Command Word
Bits
Name
Description
31:26
25
24
23:20
19:16
Specific
Interrupt Mask
SI
M
CUC
RUC
Specific Interrupt Mask. Setting this bit to 1b causes the 82551QM to stop
generating an interrupt (in other words, de-assert the INTA# signal) on the
corresponding event.
Software Generated Interrupt. Setting this bit to 1b causes the 82551QM
to generate an interrupt. Writing a 0b to this bit has no effect.
Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82551QM will not
assert its INTA# pin. The M bit has higher precedence that the Specific
Interrupt Mask bits and the SI bit.
Command Unit Command. This field contains the CU command.
Receive Unit Command. This field contains the RU command.
10.1.3
System Control Block General Pointer
The System Control Block (SCB) General Pointer is a 32-bit field that points to various data
structures depending on the command in the CU Command or RU Command field.
10.1.4
PORT
The PORT interface allows software to perform certain control functions on the 82551QM. This
field is 32 bits wide:
• Address and Data (bits 32:4)
• PORT Function Selection (bits 3:0)
The 82551QM supports four PORT commands: Software Reset, Self-test, Selective Reset, and
Dump.
10.1.5
Flash Control Register
The Flash Control Register is a 32-bit field that allows access to an external Flash device.
Datasheet
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