82551QM Datasheet, PDF (55/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
9.0
Configuration Registers
The 82551QM acts as both a master and a slave on the PCI bus. As a master, the 82551QM
interacts with the system main memory to access data for transmission or deposit received data. As
a slave, some 82551QM control structures are accessed by the host CPU to read or write
information to the on-chip registers. The CPU also provides the 82551QM with the necessary
commands and pointers that allow it to process receive and transmit data.
9.1
Function 0: LAN (Ethernet) PCI Configuration Space
The 82551QM PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in Figure 15.
Figure 15. PCI Configuration Registers
Device ID
Vendor ID
Status
Command
Class Code
Revision ID
BIST
Header Type
Latency Timer
Cache Line Size
CSR Memory Mapped Base Address Register
CSR I/O Mapped Base Address Register
Flash Memory Mapped Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Reserved (PCI mode)/CIS Pointer (CardBus mode)
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address Register
Reserved
Cap_Ptr
Reserved
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Power Management Capabilities
Next Item Ptr
Capability ID
Reserved
Data
Power Management CSR
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
DCh
E0h
9.1.1
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82551QM are both read only word entities. Their values are:
Vendor ID: 8086h
Device ID: 1229h (deskside/server)
Device ID 1059h (mobile)
Datasheet
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