82551QM Datasheet, PDF (28/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
System Error: The 82551QM reports parity error during the address phase using the SERR# pin.
If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response
bit is not set, the 82551QM only sets the Detected Parity Error bit (PCI Configuration Status
register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the 82551QM sets
the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected
Parity Error bit and asserts SERR# for one clock.
Note: The 82551QM detects a system error for any parity error during an address phase, whether or not it
is involved in the current transaction.
5.2.1.2
Bus Master Operation
As a PCI Bus Master, the 82551QM initiates memory cycles to fetch data for transmission or
deposit received data and to access the memory resident control structures. The 82551QM
performs zero wait state burst read and write cycles to the host main memory. Figure 7 and Figure
8 depict memory read and write burst cycles. For bus master cycles, the 82551QM is the initiator
and the host main memory (or the PCI host bridge, depending on the configuration of the system) is
the target.
Figure 7. Memory Read Burst Cycle
CLK
1
2
3
4
5
6
7
8
9
10
FRAME#
AD
ADDR
DATA DATA DATA DATA DATA
C/BE#
MR
BE#
BE#
IRDY#
TRDY#
DEVSEL#
22
Datasheet