82551QM Datasheet, PDF (22/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
Table 11. Initialization Effects
Internal
POR
Power
management
?
event reset
Statistic
counters reset
?
Sampling of
configuration
?
input pins
ALTRST#
RST#
ISOLATE#
D3 to D0
Transition
Software
Reset
Clear only Clear only
if no
if no
?
auxiliary auxiliary
--
--
power
power
present present
Selective
Reset
--
?
?
?
?
?
--
?
?
--
--
--
--
5.1.2
Initialization Effects on TCO Functionality
The 82551QM has the ability to be controlled by two masters, the host CPU on the PCI bus and the
TCO controller on the SMB. The 82551QM may be initialized by the PCI bus during SMB
operation. The table below lists the effect of those sources:
Table 12. Initialization Effects on TCO
Initialization Source
SMB Behavior
Status and Receive
Enable
ALTRST#, RST#, or
ISOLATE#^a
The SMB is terminated instantaneously.^b
Initialized to inactive
D3 to D0 transition
The SMB cycle is aborted. During SMB read
commands, the 82551QM transfers zeros until the
end of the cycle. An SMB write cycle has no effect on
the 82551QM. The 82551QM asserts the
SMB_ALERT# after a D3 to D0 transition. The
82551QM indicates its initialization status to the TCO
controller via an active initialization bit in the Status
Word.
Initialized to inactive
Software Reset,
Selective Reset, or D3 to
D0 transition
The SMB cycle is aborted. During SMB read
commands, the 82551QM transfers zeros until the
end of the cycle. An SMB write cycle has no effect on
the 82551QM. After a software reset, the 82551QM
reports its initialization in the same manner as in a D3
to D0 transition.
Unaffected
a. ISOLATE# acts as reset on its trailing edge. While the 82551QM is in the D3 power state, the RST# initializes the
82551QM on the trailing edge.
b. SMB commands in process will be terminated immediately.
5.2
5.2.1
PCI and CardBus Interface
Bus Operations
After configuration, the 82551QM is ready for its normal operation. As a Fast Ethernet Controller,
the role of the 82551QM is to access transmitted data or deposit received data. In both cases the
82551QM, as a bus master device, will initiate memory cycles by way of the PCI bus.
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Datasheet