82551QM Datasheet, PDF (60/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
in a device independent manner, the base registers for this mapping are placed in the predefined
header portion of configuration space. Device drivers can then access this configuration space to
determine the mapping of a particular device.
Figure 19. Base Address Register for Memory Mapping
31
Base Address
Prefetchable
The prefetchable bit is set to “0”
Type
00 - locate anywhere in 32-bit address space
01 - locate below 1 MB
10 - locate anywhere in 64-bit address space
11 - reserved
Memory space indicator
43210
0
Figure 20. Base Address Register for I/O Mapping
31
Base Address
Reserved
I/O space indicator
210
01
Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory
or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that
map to I/O space must return 1b in bit 0.
Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is
reserved and must return 0b on reads, and the other bits are used to map the device into I/O space.
The number of upper bits that a device actually implements depends on how much of the address
space the device will respond to. For example, a device that wants a 1 MB memory address space
would set the most significant 12 bits of the base address register to be configurable, setting the
other bits to 0b.
The 82551QM contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.
9.1.9.1
CSR Memory Mapped Base Address Register
The 82551QM requires one BAR for memory mapping. Software determines which BAR, memory
or I/O, is used to access the 82551QM CSR registers.
The memory space for the 82551QM CSR Memory Mapped BAR is 4 KB. The space is marked as
not prefetchable and is mapped anywhere in the 32-bit memory address space.
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Datasheet