82551QM Datasheet, PDF (31/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

5.2.2
5.2.3
Networking Silicon — 82551QM
• When the arbitration counter’s feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82551QM switches to
other pending DMAs on cache line boundary only.
This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance. If this feature is used, it is recommended that the CLS
register in PCI Configuration space is set to 8 or 16.
5.2.1.2.3 Error Handling
Data Parity Errors: As an initiator, the 82551QM checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register,
bit 6), the 82551QM also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82551QM during read cycles, it
sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
Clock Run Signal
The CLK_RUN# signal is used to control the PCI clock as defined in the CardBus specification
and PCI Mobile design guide and is compliant with both the CardBus specification and PCI Mobile
design guide. This signal is active in both the CardBus and PCI bus operating modes. The Clock
Run signal is an open drain I/O signal. It is used as a bidirectional channel between the host and the
devices.
• The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
• The host asserts the CLK_RUN# signal when the clock is either running at a normal operating
frequency or about to be started.
• The 82551QM asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the
host from stopping or to request that the host restore the clock if it was previously stopped.
Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN#
assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase
in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In
this case, the 82551QM claims the PCI clock even during idle time. If the CLK_RUN# signal is not
used, it must be connected to a pull-down resistor.
Power Management Event and Card Status Change Signals
The 82551QM supports power management indications in the PCI and CardBus mode. In CardBus
systems, the CSTSCHG pin is used for power management event indication. The PME# output pin
provides an indication of a power management event in PCI systems. The CSTSCHG pin is
supported by four registers located in the Control/Status Register (Section 10.0, “Control/Status
Registers” describes these registers in more detail).
Datasheet
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