82551QM Datasheet, PDF (27/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
5.2.1.1.3 Retry Premature Accesses
The 82551QM responds with a Retry to any configuration cycle accessing the 82551QM before the
completion of the automatic read of the EEPROM. The 82551QM may continue to Retry any
configuration accesses until the EEPROM read is complete. The 82551QMdoes not enforce the
rule that the retry master must attempt to access the same address again to complete any delayed
transaction. Any master access to the 82551QM after the completion of the EEPROM read will be
honored. Figure 6 below depicts how a Retry looks when it occurs.
Figure 6. PCI Retry Cycle
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
Note: The 82551QM is considered the target in the above diagram; thus, TRDY# is not asserted.
A Retry may also occur in the following two scenarios:
• Card Information Structure (CIS) in memory is accessed in CardBus mode.
• External modem registers are accessed and the modem does not assert IOCHRDY within 7
PCI clocks from the assertion of MDMCS#.
5.2.1.1.4 Error Handling
Data Parity Errors: The 82551QM checks for data parity errors while it is the target of the
transaction. If an error was detected, the 82551QM always sets the Detected Parity Error bit in the
PCI Configuration Status register, bit 15. The 82551QM also asserts PERR#, if the Parity Error
Response bit is set (PCI Configuration Command register, bit 6). The 82551QM does not attempt
to terminate a cycle in which a parity error was detected. This gives the initiator the option of
recovery.
Target-Disconnect: The 82551QM prematurely terminates a cycle in the following cases:
• After accesses to the Flash buffer
• After accesses to its CSR
• After accesses to the configuration space
Datasheet
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