82551QM Datasheet, PDF (57/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
Table 15. PCI Command Register Bits
Bits
Name
Description
2
Bus Master
1
Memory Space
0
I/O Space
This bit controls a device’s ability to act as a master on the PCI bus. A
value of 0b disables the device from generating PCI accesses. A value of
1b allows the device to behave as a bus master. In the 82551QM, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to the memory space accesses. A
value of 0b disables the device response. A value of 1b allows the device
to respond to memory space accesses. In the 82551QM, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to the I/O space accesses. A value of
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82551QM, this bit is configurable
and has a default value of 0b.
9.1.3
PCI Status Register
The 82551QM Status register is used to record status information for PCI bus related events. The
format of this register is shown in the figure below.
Figure 17. PCI Status Register
31 30 29 28 27 26 25 24 23 22 21 20 19
16
0 0 01 1 0 0 1 Reserved
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Parity Error Detected
Fast Back To Back (target)
Capabilities List
Note: Bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits
are described in the table below.
Table 16. PCI Status Register Bits
Bits
31
30
29
Name
Description
Detected Parity Error
This bit indicates whether a parity error is detected. This bit must be set by
the device when it detects a parity error, even if parity error handling is
disabled (as controlled by the Parity Error Response bit in the PCI
Command register, bit 6). In the 82551QM, the initial value of the Detected
Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates when the device has asserted SERR#. In the 82551QM,
Signaled System Error the initial value of the Signaled System Error bit is 0b. This bit is set until
cleared by writing a 1b.
Received Master
Abort
This bit indicates whether or not a master abort has occurred. This bit must
be set by the master device when its transaction is terminated with a
master abort. In the 82551QM, the initial value of the Received Master
Abort bit is 0b. This bit is set until cleared by writing a 1b.
Datasheet
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