82551QM Datasheet, PDF (26/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
Figure 5. Flash Buffer Write Cycle
CLK
FRAME#
AD
ADDR
C/BE#
MEM WR
IRDY#
TRDY#
DEVSEL#
STOP#
DATA
BE#
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the
82551QM with valid data immediately after asserting IRDY#. The 82551QM controls the TRDY#
signal and de-asserts it for a certain number of clocks until valid data is written to the Flash buffer.
By asserting TRDY#, the 82551QM signals the CPU that the current data access has completed.
Flash buffer write accesses can be byte length only.
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Datasheet