82551QM Datasheet, PDF (24/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
Figure 2. CSR I/O Read Cycle
CLK
1
2
3
4
5
6
7
8
9
FRAME#
AD
ADDR
DATA
C/BE#
I/O RD
BE#
IRDY#
TRDY#
DEVSEL#
STOP#
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551QM
controls the TRDY# signal and provides valid data on each data access. The 82551QM allows the
CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY#
when it is not ready.
Figure 3. CSR I/O Write Cycle
CLK
1
2
3
4
5
6
7
8
9
FRAME#
AD
ADDR
DATA
C/BE#
I/O WR
BE#
IRDY#
TRDY#
DEVSEL#
STOP#
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Datasheet