82551QM Datasheet, PDF (36/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
The following tables list the functionality at the different power states for the 82551QM.
Table 13. Functionality at the Different Power States
Power State
Link
Functionality
D0u
Don’t care
Valid
D0a
Invalid
Valid
D1
Invalid
Valid
D2
Invalid
Valid
D3 (with power)
Invalid
Dx (x>0 without
PME#)
Don’t care
• Power-up state
• PCI slave access
Full functionality at full power and wake on an
invalid link
Full functionality at full power and wake on a valid
link
• Wake-up on “interesting” packets and link
invalid
• PCI configuration access
• Wake on link valid
• PCI configuration access
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
No wake-up functionality
Note: If the TCO bit is set in the EEPROM, the
82551QM will not disable the link function and will
consume power as in the D2 state.
5.3.2
Wake-up Events
There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two
events are detailed below.
Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/
Status (PMCSR) register is set. The PMCSR is described in Section 9.1.21, “Power Management
Control/Status Register (PMCSR)”.
5.3.2.1
“Interesting” Packet Event
In the power-down state, the 82551QM is capable of recognizing “interesting” packets. The
82551QM supports pre-defined and programmable packets that can be defined as any of the
following:
• Address Resolution Protocol (ARP) Packets (with Multiple IP addresses)
• Direct Packets (with or without type qualification)
• Magic Packet*
• Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment)
• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
• Internetwork Package Exchange* (IPX*) Diagnostic Packet
• TCO Packet
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Datasheet