82551QM Datasheet, PDF (79/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
Table 35. LAN Function Present State Register
Bits Function Default
Description
3
Reserved 0b
2
Reserved 0b
1
Reserved 0b
0
Reserved 0b
Bit 3 is reserved in the CardBus Specification.
Reserved.
Reserved.
Bit 0 is reserved in the CardBus Specification.
10.1.13.4 LAN Force Event Register
The Force Event register simulates status change events for troubleshooting purposes. This register
provides the ability to simulate events by forcing values into the Function Event register.
Table 36. LAN Force Event Register
Bits
31:16
15
14:5
4
3:0
Function Default
Reserved 0
INTR
0
Reserved 0
GWAKE 0
Reserved 0
Description
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. Writing 1b in this field will set the interrupt
bit in the LAN Function Event register. If the INTA# pin is not masked,
then it will also be activated. Writing 0b has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. Writing 1b in this field will set the
CSTSCHG bit in the LAN Function Event register. If the CSTSCHG pin
is not masked, then it will also be activated. Writing 0b has no effect.
Bits [3:0] are reserved in the CardBus Specification.
10.2
Statistical Counters
The 82551QM provides information for network management statistics by providing on-chip
statistical counters that count a variety of events associated with both transmit and receive. The
counters are updated by the 82551QM when it completes the processing of a frame (that is, when it
has completed transmitting a frame on the link or when it has completed receiving a frame). The
Statistical Counters are reported to the software on demand by issuing the Dump Statistical
Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit
Command (CUC) field.
Table 37. Statistical Counters
ID
Counter
Description
0 Transmit Good Frames
4
Transmit Maximum Collisions
(MAXCOL) Errors
8
Transmit Late Collisions
(LATECOL) Errors
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory, as is done for the Transmit
Command Block status.
This counter contains the number of frames that were not
transmitted because they encountered the configured
maximum number of collisions.
This counter contains the number of frames that were not
transmitted due to an encountered collision after the
configured slot time.
Datasheet
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