82551QM Datasheet, PDF (63/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
The 82551QM provides support for configurable Subsystem Vendor ID and Subsystem ID fields.
After hardware reset is de-asserted, the 82551QM automatically reads addresses Ah through Ch of
the EEPROM. The first of these 16-bit values is used for controlling various 82551QM functions.
The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the
default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively.
The 82551QM checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions
according to Table 19 below.
Table 19. ID Fields Programming
Signature
ID
AltID
(Bits 15:14) (Bit 13) (Bit 7)
11b^b, 10b,
00b
X
X
01b
1b
X
01b
0b
1b
01b
0b
0b
Device Vendor Revision ID^a
ID
ID
(A-0 and A-1)
1229h 8086h 0Fh
1229h
1229h
1229h
8086h
8086h
8086h
Word Ah, bits
10:8
0Fh
0Fh
Subsystem Subsystem
ID
Vendor ID
0000h
0000h
Word Bh
Word Bh
Word Bh
Word Ch
Word Ch
Word Ch
a. The Revision ID is subject to change according to the silicon stepping.
b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
The above table implies that if the 82551QM detects the presence of an EEPROM (as indicated by
a value of 1b in bits 15 and 14), then bit number 13 determines whether the values read from the
EEPROM, words Bh and Ch, are loaded into the Subsystem ID (word Bh) and Subsystem Vendor
ID (word Ch) fields. If bits 15 and 14 equal 1b and bit 13 equals 1b, the three least significant bits
of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah.
Between the de-assertion of reset and the completion of the automatic EEPROM read, the
82551QM does not respond to any PCI configuration cycles. If the 82551QM happens to be
accessed during this time, it will Retry the access. More information on Retry is provided in
Section 5.2.1.1.3, “Retry Premature Accesses”.
9.1.13
Capability Pointer
The Capability Pointer is a hard-coded byte register with a value of DCh. It provides an offset
within the Configuration Space for the location of the Power Management registers.
9.1.14
Interrupt Line Register
The Interrupt Line register identifies which system interrupt request line on the interrupt controller
the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.
9.1.15
Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
INTA# through INTD#, a PCI device is connected to. The 82551QM is connected the INTA# pin.
Datasheet
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