82551QM Datasheet, PDF (6/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
11.0
PHY Unit Registers .......................................................................................................... 79
11.1 MDI Registers 0 - 7 ............................................................................................. 79
11.1.1 Register 0: Control Register .................................................................. 79
11.1.2 Register 1: Status Register ................................................................... 80
11.1.3 Register 2: PHY Identifier Register ....................................................... 81
11.1.4 Register 3: PHY Identifier Register ....................................................... 81
11.1.5 Register 4: Auto-Negotiation Advertisement Register ........................... 81
11.1.6 Register 5: Auto-Negotiation Link Partner Ability Register .................... 82
11.1.7 Register 6: Auto-Negotiation Expansion Register ................................. 82
11.2 MDI Registers 8 - 15 ........................................................................................... 82
11.3 MDI Register 16 - 31 ........................................................................................... 83
11.3.1 Register 16: PHY Unit Status and Control Register .............................. 83
11.3.2 Register 17: PHY Unit Special Control Register ................................... 83
11.3.3 Register 18: PHY Address Register ....................................................... 84
11.3.4 Register 19: 100BASE-TX Receive False Carrier Counter ................... 84
11.3.5 Register 20: 100BASE-TX Receive Disconnect Counter ...................... 85
11.3.6 Register 21: 100BASE-TX Receive Error Frame Counter .................... 85
11.3.7 Register 22: Receive Symbol Error Counter ......................................... 85
11.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Coun-
ter 85
11.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter ............. 85
11.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter ..................... 86
11.3.11 Register 26: Equalizer Control and Status Register .............................. 86
11.3.12 Register 27: PHY Unit Special Control Register ................................... 86
11.3.13 Register 28: MDI/MDI-X Control Register .............................................. 87
11.3.14 Register 29: Hardware Integrity Control Register .................................. 87
12.0
Electrical and Timing Specifications................................................................................. 89
12.1 Absolute Maximum Ratings ................................................................................ 89
12.2 DC Specifications ............................................................................................... 90
12.3 AC Specifications ................................................................................................ 93
12.4 Timing Specifications .......................................................................................... 94
12.4.1 Clocks Specifications ............................................................................. 94
12.4.2 Timing Parameters ................................................................................. 95
13.0
82551QM Test Port Functionality................................................................................... 103
13.1 Introduction ....................................................................................................... 103
13.2 Test Function Description ................................................................................. 103
13.2.1 Tristate ................................................................................................. 103
13.2.2 XOR Tree ............................................................................................. 104
14.0
Package and Pinout Information .................................................................................... 107
14.1 Package Information ......................................................................................... 107
14.2 Pinout Information ............................................................................................. 109
14.2.1 Pin Assignments ................................................................................. 109
14.2.2 Ball Grid Array Diagram ....................................................................... 111
15.0
Reference Schematics ................................................................................................... 112
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Datasheet