82551QM Datasheet, PDF (25/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the
82551QM with valid data on each data access immediately after asserting IRDY#. The 82551QM
controls the TRDY# signal and asserts it from the data access. The 82551QM allows the CPU to
issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting
the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
5.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow and the 82551QM issues a target-disconnect at
the first data access. The 82551QM asserts the STOP# signal to indicate a target-disconnect. The
figures below illustrate memory CPU read and write accesses to the 128 KB Flash buffer. The
longest burst cycle to the Flash buffer contains one data access only.
Figure 4. Flash Buffer Read Cycle
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
ADDR
MEM RD
DATA
BE#
STOP#
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM controls
the TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from
the Flash buffer. When TRDY# is asserted, the 82551QM drives valid data on the AD[31:0] lines.
The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read
accesses can be byte or word length.
Datasheet
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