82551QM Datasheet, PDF (71/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
10.0 Control/Status Registers
10.1
LAN (Ethernet) Control/Status Registers
The 82551QM’s Control/Status Register (CSR) is illustrated in the Table 22.
Figure 22. Control/Status Register
D31
Upper Word
D16
D15
Lower Word
D0
SCB Command Word
SCB Status Word
System Control Block General Pointer
PORT
EEPROM Control Register
Flash Control Register
Management Data Interface (MDI) Control Register
Receive Direct Memory Access Byte Count
PMDR
Flow Control Register
Reserved
Reserved
General Status
General Control
Reserved
Command Block Pointer
Reserved
Reserved
Function Event Register
Function Event Mask Register
Function Present State Register
Force Event Register
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
NOTE: In Figure 22 above, SCB is defined as the System Control Block of the 82551QM, and PMDR is defined
as the Power Management Driver Register.
SCB Status Word: The 82551QM places the status of its Command and Receive units and
interrupt indications in this register for the CPU to read.
SCB Command Word: The CPU places commands for the Command and Receive units in this
register. Interrupts are also acknowledged in this register.
SCB General Pointer: The SCB General Pointer register points to various data structures in main
memory depending on the current SCB Command word.
PORT Interface: The PORT interface allows the CPU to reset the 82551QM, force the 82551QM
to dump information to main memory, or perform an internal self test.
Flash Control Register: The Flash Control register allows the CPU to enable writes to an external
Flash.
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
an external EEPROM.
Datasheet
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